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oki semiconductor fedl63611a-01 issue date: jan. 28, 2004 ml63611a 4-bit microcontroller that operates under ultra- low supply current, with rc oscillation type a/d converter built-in 1/49 general description the ml63611a is a cmos 4-bit microcontroller using oki?s original cpu core nx-4/250. the ml63611a is provided with the mask options of eight items of selection including (1.5 v or 3.0 v) power supply specifications and (with or without) the re gulator circuit for the lcd bias reference voltage. when a 3.0 v power supply specification is selected, the halver circuit can be used to decrease power consumption. the halver circuit cannot be used when a 1.5 v power supply specification is selected. when ?with the regulator circuit for the lcd bias re ference voltage? is selected, the lcd bias reference voltage will be generated based on the output voltage of the regulator circuit. when ?without the regulator circuit for the lcd bias reference voltage? is select ed, the lcd bias reference voltage will be generated based on the power supply voltage; for this reason, the lcd bias voltage decreases as the power supply voltage decreases, causing the display density of the lcd panel to thin down. the ml63611a has incorporated in it an 8k-word program memory, a 1k-nibble data memory, four input ports, four output ports (only when the mask option of lcd driver pins is selected), 16 i/o ports, a melody circuit, a serial port, four 8-bit timers, and a 64-segment lcd driver (60 segment lines and 4 common lines, max.). (a part of the seg pins can also be selected as output port pins or com pins depending on the mask option.) note: in this datasheet, for convenience of description, t he symbols option a, option b, option c, and option d are used in accordance with the mask option sele ction of a power supply specification (1.5 v or 3.0 v) and the regulator circuit for the lcd bias refe rence voltage (with or wi thout), as shown below. ? option a: 1.5 v power supply specification (halver ci rcuit disabled), without the regulator circuit for the lcd bias reference voltage ? option b: 1.5 v power supply spec ification (halver circuit disabled), with the regulator circuit for the lcd bias reference voltage ? option c: 3.0 v power supply specification (halver ci rcuit enabled), without the regulator circuit for the lcd bias reference voltage ? option d: 3.0 v power supply spec ification (halver circuit enabled), wi th the regulator circuit for the lcd bias reference voltage features the ml63611a has the following features. a. extensive instruction set ? 407 instructions transfer, rotate, increment/decrem ent, arithmetic operations, comp are, logic operations, mask operations, bit operations, rom table reference, stack operations, flag operations, jump, conditional branch, call/return, control b. wide variety of addressing modes ? indirect addressing mode for 4 types of data memory with current bank register, extra bank register, hl register and xy register ? data memory bank internal direct addressing mode !
fedl63611a-01 oki semiconductor ml63611a 2/49 c. processing speed x 2 clocks per machine cycle, with most instructions executed in 1 machine cycle x minimum instruction execution time: 61 s (@ 32.768 khz system clock) 10 s (@ 200 khz system clock) 2.86 s (@ 700 khz system clock) d. clock generator circuit x low-speed clock: crystal oscillation (32.768 khz) x high-speed clock: option a, option b: rc oscillation (200 khz max.) option c, option d: ceramic oscillation or rc oscillation selected with software (700 khz max.) e. program memory space x 8k words x the basic instruction length is 16 bits per word. f. data memory space x 1024 nibbles g. stack level x call stack level: 16 x register stack level: 16 h. ports input port (port 0.0 to port 0.3): selectable as input with pull-up resistor/high-impedance input provided with the reset function that resets the system when there is a simultaneous key depression of multiple bits (2, 3, or 4 bits). output port: selectable as n-channel open drain output/cmos output enabled only when the seg pins (l32 to l3 5) are selected as the output port by the mask option. input-output port (port a.0 to port a.3, port b.0 to po rt b.3, port c.0 to port c.3, port e.0 to port e.3): selectable as input with pull- up resistor/input with pull-down resistor/high-impedance input selectable as p-channel open drain output/n-channel open drain output/cmos output/high-impedance output number of ports: input ports output ports input-output ports chip products 1 port u 4 bits 1 port u 4 bits 4 ports u 4 bits (mask option) i. melody output x melody frequency: 529 hz to 2979 hz (@ 32.768 khz) x tone length: 63 varieties x tempo: 15 varieties x melody data: stored in program memory x buzzer driver signal output: 4 khz (@ 32.768 khz)
fedl63611a-01 oki semiconductor ml63611a 3/49 j. lcd driver segment-type lcd drivers built-in the following pin modes can be specified for l0 to l63 by the mask option generator setting. (refer to the ?mogtool mask option generator user?s manual?.) ? z ? in the table below indicates that that particular function can be selected. l0 to l3 l4 to l31 l32 to l35 l36 to l39 l40 to l63 seg pins z z z z z com pins z *1 ? ? z *1 ? output port pins ? ? z *2 ? ? *1 can be selected as a com pin in 1-bit unit (l0 to l3, l36 to l39). a maximum of four pins can be selected as com pins. *2 can be selected as an output port in 4-bit unit (l32 to l35). n-channel open drain out put or cmos output can be specified for each bit. number of segments : 64 (60 seg. u 4 com. max.) duty : 1/1 to 1/4 duty (fixed to 1/2 duty when at 1/2 bias) bias : selectable as 1/2 or 1/3 bias (s electable by the mask option. refer to the ?mogtool mask option generator user?s manual?.) option b, option d: regulator circuit used (0.95/1.90/2.85 v) option a, option c: regulator circu it not used (directly connected to the power supply voltage (1.5/3.0/4.5 v)) frame frequency : 64 hz (at 1/1, 1/2, 1/4 duty), 85.3 hz (at 1/3 duty) contrast : option b, option d: adjustable up to 16 levels (in steps of 0.03 v) option a, option c: adjustment not available display modes : selectable as all-on mode/a ll-off mode/power down mode/normal display mode k. rc oscillation type a/d converter x 2 channels (time sharing is used) l. system reset function x system reset by reset pin (2 khz sampling function provided) x system reset that resets the system when the combined bits (2, 3, or 4 bits) of the input port (port 0) are all set to a ?h? level (whether system reset is disabled or enabled, the number of bits to be combined, and the polarity can be specified by mask option. refer to the ?mogtool mask option generator user?s manual?.) 2 bits : p0.0, p0.1 3 bits : p0.0, p0.1, p0.2 4 bits : p0.0, p0.1, p0.2, p0.3 m. battery check x applies to the option c and option d. does not apply to the option a and option b. x function that detects battery low voltage x selection of judgment volta ge by software (ld1 and ld0 bit settings of bldcon) x judgment voltage 1.80 r 0.10 v, 2.00 r 0.10 v,2.40 r 0.10 v, 2.60 r 0.10 v(ta = 25 q c)
fedl63611a-01 oki semiconductor ml63611a 4/49 n. timers, counters x 8-bit timer: 4 channels selectable as auto-reload mode, capture mode, clock frequency measurement mode x watchdog timer: 1 channel x 100 hz timer: 1 channel 1/100 sec. measurement possible x 15-bit tbc: 1 channel 1 hz, 2 hz, 4 hz, 8 hz, 16 hz, 32 hz, 64 hz, 128 hz signals can be read o. serial port x mode: uart mode, synchronous mode x communication speed in uart mode: 1200 bps, 2400 bps, 4800 bps, 9600 bps x clock frequency in synchronous mode: 32.768 khz (internal clock mode); external clock frequency x data length: 5 to 8 bits p. interrupt factors x external interrupt (4 sources) : selectable as rising edge/falling edge/both rising and falling edges x internal interrupt (14 sources) : watchdog timer interrupt u 1 melody end interrupt u 1 adc interrupt u 1 timer interrupt u 4 serial port reception interrupt u 1 serial port transmission interrupt u 1 1/100 timer (10 hz) interrupt u 1 time base interrupt u 4 (2, 4, 16, and 32 hz) q. operating temperature x ?20 to +70 q c r. power supply voltage option a, option b (1.5 v versions): 1.3 to 1.7 v note: the operation will only be at the battery voltage and no voltage halver circuit can be used. option c, option d (3.0 v versions): 1.8 to 3.6 v note: it is possible to select by software to use the output of the halver ci rcuit as the power supply of the voltage regulator circuit when the battery voltage is in the range 2.4 to 3.6 v, and to use the battery voltage itself as the power supply of the voltage regulator circuit when the battery voltage is in the range 1.8 to 2.4 v. it is possible to detect whether the battery voltage is 2.4 v or 1.8 v using the bld function. ? when the halver circuit is on: 2.4 to 3.6 v ? when the halver circuit is off: 1.8 to 2.4 v
fedl63611a-01 oki semiconductor ml63611a 5/49 s. supply current x in the halt mode, with the lcd display off, low-speed operation, ?20 to +70 q c: option a (1.5 v power supply specification, w ithout the regulator circuit for the lcd bias reference voltage): typ. 1.4 p a / max. 2.8 p a option b (1.5 v power supply specification, with the regulator circuit for the lcd bias reference voltage): typ. 1.6 p a / max. 3.0 p a option c (3.0 v power supply specification, w ithout the regulator circuit for the lcd bias reference voltage): typ. 0.53 p a / max. 1.2 p a option d (3.0 v power supply specification, with the regulator circuit for the lcd bias reference voltage): typ. 0.70 p a / max. 1.4 p a t. packages available package product name chip (116-pad) ML63611A-XXXWA (here, ?xxx? denotes the code number.)
fedl63611a-01 oki semiconductor ml63611a 6/49 mask options there are nine items in the mask option of the ml63611a. make the settings for the following items using th e mogtool mask option ge nerator. refer to the ?mogtool mask option generator us er?s manual? for details of th e method of making the settings. 1) selection of power supply voltage select a power supply specification for the power su pply voltage to be used as either a 1.5 v power supply specification (1.3 to 1.7 v) or a 3.0 v power supply specification (1.8 to 3.6 v). note: when a 1.5 v power supply specificat ion (option a and option b) is selected, the halver circuit and the battery low detect circuit cannot be used. 2) selection of the regulator circuit for the lcd bias reference voltage select the lcd bias reference voltage as either th e output of the regulator circuit or the power supply voltage. note: when power is supplied from the battery: when ?without the regulator circuit fo r the lcd bias reference voltage? is selected with the mask option, the lcd bias reference voltage will be generated based on the power supply voltage. when a 1.5 v power supply specification is selected, v dd1 will be the pin for the lcd bias re ference voltage, and when a 3.0 v power supply specification is selected, v dd2 will be the pin for the lcd bias refe rence voltage. in addition, the lcd bias voltage will decrease as the pow er supply voltage decreases, causi ng the display density of the lcd panel to thin down. when ?with the regulator circuit for the lcd bias referenc e voltage? is selected, the di splay density will be kept constant even if the ba ttery voltage decreases. 3) selection of the initial state of port 0 select the initial state of port 0 as either ?input with pull-down resistor? or ?input with pull-up resistor?. this selection determines the initial value of p0pud (p0con1). note: this selection applies to all four bits and it is not possible to make this selection separately for each bit. 4) selection of simultaneous key de pression reset function of port 0 select the simultaneous key depression reset function and the number of bits (pins) that can be pressed simultaneously. the pins that are set according to the number of bits pressed simultaneously are fixed as follows: 2 bits: p0.0, p0.1; 3 bits: p0.0, p0.1 , p0.2; 4 bits: p0.0, p0.1, p0.2, p0.3. note: the system reset mode will be entered at the second falling edge of the 1 hz signal. 5) selection of mdb pin output voltage level select whether to make the output voltage level of the melody output pin (mdb: negative logic) either v dd or v ss when the melody is off. ! ! ! !
fedl63611a-01 oki semiconductor ml63611a 7/49 6) seg/com/port/data selection of the lcd driver pins it is possible to make the pins l0 to l3 and l36 to l39 either seg pins or com pins. however, it is a maximum of four pins that can be selected as com pins. it is possible to make the pins l32 to l35 either seg pins or output port pins. the pins l4 to l31 and l40 to l63 are always seg pins. the segment register corresponding to the pins l0 to l63 can also be used as a data area. notes: ? when the selection is made as output port pi ns, the selection applies to all four bits. ? when the segment register is se lected as the data area, the corre sponding pins will still be outputting the segment waveforms, and hence should be left open. 7) selection of the register address and data of the lcd driver pins the allocation of the register address a nd data is set for each lcd driver pin. note: it is not possible to make multiple settings for the sa me address and the same bit. 8) selection of whether or not to detect stoppage of low-speed clock oscillations select whether or not to detect stoppage of the low- speed clock oscillations and to transfer to the system reset mode. 9) selection of the lcd bias 1/3 or 1/2 bias is selected for the lcd bias. note: the setting of the mask option should ma tch the setting of bit 3 of display co ntrol register 0. otherwise, normal waveforms are not output. ! ! !
fedl63611a-01 oki semiconductor ml63611a 8/49 block diagram figures 1 through 4 show the block diagram of option a to d asterisks ( * ) indicate the port secondary functions. figure 1 option a block diagram cpu core : nx-4/250 timing con- trol cbr ebr h l x y ra mie a instruction decoder ir bus con- trol rom (8 kw) sp rsp c g z stack cal.s:16 levels reg.s:16 levels pc a lu ram (1 kn) int tbc rst tst xt0 xt1 xt rese t tm0cap/tm1cap* timer (8-bit, 4ch) tm0ovf/tm1ovf* t02ck* t13ck* sio (sync/async) rxc* txc* melod y md int 4 txd* lcd & dspr l0 to l63 int 4 tst2 data bus wdt int 1 tst1 mdb 100hztc int 1 bias v ss input port int 1 p0.0 to p0.3 i/o port int 3 int 1 int 2 v/h pa.0 to pa.3 pb.0 to pb.3 v dd3 v dd2 v dd1 c1 c2 (open) v hf (open) hc1 (open) hc2 v/r2 v ch v/r1 osc0 osc1 osc tbcclk* output port lp0.0 to lp0.3 (mask option of lcd segments) rxd* pc.0 to pc.3 pe.0 to pe.3 a dc rt0 crt0 rs0 cs0 in0 rt1 rs1 cs1 in1 int 1 mon* hsclk* v dd
fedl63611a-01 oki semiconductor ml63611a 9/49 figure 2 option b block diagram cpu core : nx-4/250 timing con- trol cbr ebr h l x y ra mie a instruction decoder ir bus con- trol rom (8 kw) sp rsp c g z stack cal.s:16 levels reg.s:16 levels pc a lu ram (1 kn) int tbc rst tst xt0 xt1 xt rese t tm0cap/tm1cap* timer (8-bit, 4ch) tm0ovf/tm1ovf* t02ck* t13ck* sio (sync/async) rxc* txc* melod y md int 4 txd* lcd & dspr l0 to l63 int 4 tst2 data bus wdt int 1 tst1 mdb 100hztc int 1 bias v ss input port int 1 p0.0 to p0.3 i/o port int 3 int 1 int 2 v/h pa.0 to pa.3 pb.0 to pb.3 v dd3 v dd2 v dd1 c1 c2 (open) v hf (open) hc1 (open) hc2 v/r2 v ch v/r3 v/r1 osc0 osc1 osc tbcclk* output port lp0.0 to lp0.3 (mask option of lcd segments) rxd* pc.0 to pc.3 pe.0 to pe.3 a dc rt0 crt0 rs0 cs0 in0 rt1 rs1 cs1 in1 int 1 mon* hsclk* v dd
fedl63611a-01 oki semiconductor ml63611a 10/49 figure 3 option c block diagram cpu core : nx-4/250 timing con- trol cbr ebr h l x y ra mie a instruction decoder ir bus con- trol rom (8 kw) sp rsp c g z stack cal.s:16 levels reg.s:16 levels pc a lu ram (1 kn) int tbc rst tst xt0 xt1 xt rese t tm0cap/tm1cap* timer (8-bit, 4ch) tm0ovf/tm1ovf* t02ck* t13ck* sio (sync/async) rxc* txc* melod y md int 4 txd* lcd & dspr l0 to l63 int 4 tst2 data bus bld wdt int 1 tst1 mdb 100hztc int 1 bias v ss input port int 1 p0.0 to p0.3 i/o port int 3 int 1 int 2 v/h pa.0 to pa.3 pb.0 to pb.3 v dd3 v dd2 v dd1 c1 c2 v hf hc1 hc2 v/r2 v ch v/r1 osc0 osc1 osc tbcclk* output port lp0.0 to lp0.3 (mask option of lcd segments) rxd* pc.0 to pc.3 pe.0 to pe.3 a dc (use/nonuse selected by software) rt0 crt0 rs0 cs0 in0 rt1 rs1 cs1 in1 int 1 mon* hsclk*
fedl63611a-01 oki semiconductor ml63611a 11/49 figure 4 option d block diagram cpu core : nx-4/250 timing con- trol cbr ebr h l x y ra mie a instruction decoder ir bus con- trol rom (8 kw) sp rsp c g z stack cal.s:16 levels reg.s:16 levels pc a lu ram (1 kn) int tbc rst tst xt0 xt1 xt rese t tm0cap/tm1cap* timer (8-bit, 4ch) tm0ovf/tm1ovf* t02ck* t13ck* sio (sync/async) rxc* txc* melod y md int 4 txd* lcd & dspr l0 to l63 int 4 tst2 data bus bld wdt int 1 tst1 mdb 100hztc int 1 bias v ss input port int 1 p0.0 to p0.3 i / o port int 3 int 1 int 2 v/h pa.0 to pa.3 pb.0 to pb.3 v dd3 v dd2 v dd1 c1 c2 v hf hc1 hc2 v/r2 v ch v/r3 v/r1 osc0 osc1 osc tbcclk* output port lp0.0 to lp0.3 (mask option of lcd segments) rxd* pc.0 to pc.3 pe.0 to pe.3 a dc (use/nonuse selected by software) rt0 crt0 rs0 cs0 in0 rt1 rs1 cs1 in1 int 1 mon* hsclk*
fedl63611a-01 oki semiconductor ml63611a 12/49 pad configuration the ml63611a chip pin configuration and the pad coordina tes are shown in figure 5 and table 1, respectively. chip size : 5.20 mm u 5.20 mm chip thickness : 350 p m (typ.) (280 p m: available as required) coordinate origin : chip center pad hole size : 80 p m u 80 p m pad size : 90 p m u 90 p m minimum pad pitch : 115 p m number of bonding pads: 116 (t otal number of pads: 129) notes: the chip substrate voltage is v ss . do not bond pins 100 to 112 (marked by ? ?). leave them open. figure 5 ml63611a chip pin configuration (top view) ml63611 y x ( 0.0 ) l63 l62 l61 l60 l59 l58 l57 l56 l55 l54 l53 l52 l51 l50 l49 l48 l47 l46 l45 l44 l43 l42 l41 l40 l39 l38 l37 l36 rt0 crt0 rs0 cs0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 in0 34 in1 35 cs1 36 rs1 37 rt1 38 39 v dd 40 tst1 41 tst2 42 md 43 mdb 44 p0.0 45 p0.1 46 p0.2 47 p0.3 48 pa.0 49 pa.1 50 pa.2 51 pa.3 52 pb.0 53 pb.1 54 pb.2 55 pb.3 56 pc.0 57 pc.1 58 pc.2 59 pc.3 60 pe.0 61 pe.1 62 pe.2 63 pe.3 64 v ss 65 l35 l34 l33 68 l32 69 l31 70 l30 71 l29 72 l28 73 l27 74 l26 75 l25 76 l24 77 l23 78 l22 79 l21 80 l20 81 l19 82 l18 83 l17 84 l16 85 l15 86 l14 87 l13 88 l12 89 l11 90 l10 91 l9 92 l8 93 l7 94 l6 95 l5 l4 l3 98 l2 99 l1 100 l0 101 trimb5 102 trimb4 103 trimb3 104 trimdb1 105 trimb2 106 trimb1 107 trimb0 109 trimdb2 110 trim2 111 trimd 112 trim1 113 trim0 114 v dd1 115 v dd2 116 v dd3 117 c1 118 c2 119 v ch 120 v xt 121 v hf 122 hc1 123 hc2 124 v ss 125 osc1 126 osc0 127 reset 128 xt1 129 xt0 v dd no-connection pads 33 67 66 97 96 108 trim3
fedl63611a-01 oki semiconductor ml63611a 13/49 table 1 ml63611a pad coordinates chip center: x = 0, y = 0 pad no. pad name x ( p m) y ( p m) pad no. pad name x ( p m) y ( p m) 1 l63 -2109 -2454 34 in1 2474 -2119 2 l62 -1987 -2454 35 cs1 2474 -1997 3 l61 -1865 -2454 36 rs1 2474 -1876 4 l60 -1742 -2454 37 rt1 2474 -1754 5 l59 -1620 -2454 38 v dd 2474 -1517 6 l58 -1498 -2454 39 tst1 2474 -1402 7 l57 -1376 -2454 40 tst2 2474 -1287 8 l56 -1254 -2454 41 md 2474 -1157 9 l55 -1131 -2454 42 mdb 2474 -1042 10 l54 -1009 -2454 43 p0.0 2474 -912 11 l53 -887 -2454 44 p0.1 2474 -797 12 l52 -765 -2454 45 p0.2 2474 -682 13 l51 -643 -2454 46 p0.3 2474 -566 14 l50 -520 -2454 47 pa.0 2474 -448 15 l49 -398 -2454 48 pa.1 2474 -327 16 l48 -276 -2454 49 pa.2 2474 -205 17 l47 -154 -2454 50 pa.3 2474 -84 18 l46 -32 -2454 51 pb.0 2474 38 19 l45 91 -2454 52 pb.1 2474 160 20 l44 213 -2454 53 pb.2 2474 281 21 l43 335 -2454 54 pb.3 2474 403 22 l42 457 -2454 55 pc.0 2474 524 23 l41 579 -2454 56 pc.1 2474 646 24 l40 702 -2454 57 pc.2 2474 767 25 l39 824 -2454 58 pc.3 2474 889 26 l38 946 -2454 59 pe.0 2474 1010 27 l37 1068 -2454 60 pe.1 2474 1132 28 l36 1190 -2454 61 pe.2 2474 1254 29 rt0 1442 -2474 62 pe.3 2474 1375 30 crt0 1563 -2474 63 v ss 2474 1493 31 rs0 1685 -2474 64 l35 2440 1713 32 cs0 1806 -2474 65 l34 2440 1950 33 in0 2474 -2240 66 l33 1944 2440
fedl63611a-01 oki semiconductor ml63611a 14/49 table 1 ml63611a pad coordinates (continued) chip center: x = 0, y = 0 pad no. pad name x ( p m) y ( p m) pad no. pad name x ( p m) y ( p m) 67 l32 1707 2440 99 l0 -2362 1898 68 l31 1563 2440 100 trimb5 69 l30 1441 2440 101 trimb4 70 l29 1319 2440 102 trimb3 71 l28 1197 2440 103 trimdb1 72 l27 1074 2440 104 trimb2 73 l26 952 2440 105 trimb1 74 l25 830 2440 106 trimb0 75 l24 708 2440 107 trimdb2 76 l23 586 2440 108 trim3 77 l22 463 2440 109 trim2 78 l21 341 2440 110 trimd 79 l20 219 2440 111 trim1 80 l19 97 2440 112 trim0 no-connection 81 l18 -25 2440 113 v dd1 -2474 179 82 l17 -148 2440 114 v dd2 -2474 58 83 l16 -270 2440 115 v dd3 -2474 -63 84 l15 -392 2440 116 c1 -2474 -184 85 l14 -514 2440 117 c2 -2474 -305 86 l13 -636 2440 118 v ch -2474 -426 87 l12 -759 2440 119 v xt -2474 -547 88 l11 -881 2440 120 v hf -2474 -668 89 l10 -1003 2440 121 hc1 -2474 -788 90 l9 -1125 2440 122 hc2 -2474 -909 91 l8 -1247 2440 123 v ss -2474 -1042 92 l7 -1370 2440 124 osc1 -2474 -1175 93 l6 -1492 2440 125 osc0 -2474 -1296 94 l5 -1614 2440 126 reset -2474 -1461 95 l4 -1736 2440 127 xt1 -2474 -1596 96 l3 -2362 2265 128 xt0 -2474 -1921 97 l2 -2362 2143 129 v dd -2474 -2063 98 l1 -2362 2021
fedl63611a-01 oki semiconductor ml63611a 15/49 pin descriptions the basic functions of each pin of th e ml63611a are described in table 2. a symbol with a slash (/) denotes a pin that has a secondary function. refer to table 3 for secondary functions. for type, ??? denotes a power supply pin, ?i? an input pin, ?o? an output pin, and ?i/o? an input-output pin. table 2 pin description (basic functions) classification pin name pad no. i/o function v dd 38, 129 positive power supply v ss 63, 123 negative power supply v dd1 113 v dd2 114 v dd3 115 power supply pins for lcd bias voltage (internally generated): a capacitor (1.0 p f) should be connected between v dd1 and v ss , between v dd2 and v ss , and between v dd3 and v ss . for the option a, connect v dd1 with v dd ; for the option c, connect v dd2 with v dd . c1 116 c2 117 capacitor connection pins for lcd bias voltage generation: a capacitor (1.0 p f) should be connected between c1 and c2. v hf 120 power supply pin for the internal regulator: a capacitor (0.1 p f) should be connected between this pin and v ss . leave this pin open for the option a and option b. v xt 119 power supply pin for the voltage regulator circuit for low-speed oscillation: a capacitor (1.0 p f) should be connected between this pin and v ss . v ch 118 power supply pin for the voltage regulator circuit for internal logic: a capacitor c 1 (1.0 p f) should be connected between this pin and v ss. hc1 121 power supply hc2 122 ? capacitor connection pins for the halver circuit: a capacitor (0.1 p f) should be connected between hc1 and hc2. leave these pins open for the option a and option b. xt0 128 i xt1 127 o low-speed clock oscillation pins: connect a crystal between xt0 and xt1, and connect capacitor (c g ) between xt0 and v ss. osc0 125 i oscillation osc1 124 o high-speed clock oscillation pins: ceramic oscillation or rc oscillation is selected by the software. in the option a and option b, only rc oscillation is available. if ceramic oscillation is selected, connect a ceramic resonator between osc0 and osc1, and connect capacitor (c l0 , c l1 ) between osc0 and v ss and between osc1 and v ss . if rc oscillation is selected, connect external oscillation resistor (r osh ) between osc0 and osc1. tst1 39 test tst2 40 i input pins for testing: a pull-down resistor is inter nally connected to these pins.
fedl63611a-01 oki semiconductor ml63611a 16/49 table 2 pin description (basic functions) (continued) classification pin name pad no. i/o function reset reset 126 i reset input pin: 2 khz sampling circuit is equipped. holding this pin to ? h ? level for 1 ms or more puts this device into a reset state. then, setting this pin to ? l ? level starts executing an inst ruction from address 0000h. a pull-down resistor is internally connected to this pin. md 41 melody output pin (positive logic) melody mdb 42 o melody output pin (negative logic): v dd or v ss is selectable for the pin output voltage when melody output is turned off (mask option). p0.0 43 p0.1 44 p0.2 45 p0.3 46 i 4-bit input port: pull-up resistor input, pull-down resistor input, or high-impedance input is selectable for each bit. a system reset function is prov ided that resets the system when there is a simultaneous key depression of multiple bits (mask option). pa.0 47 pa.1 48 pa.2 49 pa.3 50 i/o pb.0 51 pb.1 52 pb.2 53 pb.3 54 i/o pc.0 55 pc.1 56 pc.2 57 pc.3 58 i/o pe.0 59 pe.1 60 pe.2 61 port pe.3 62 i/o 4-bit input-output ports: in input mode, pull-up resist or input, pull-down resistor input, or high-impedance input is selectable for each bit. in output mode, p-channel open drain output, n-channel open drain output, cmos output, or high-impedance output is selectable for each bit.
fedl63611a-01 oki semiconductor ml63611a 17/49 table 2 pin description (basic functions) (continued) classification pin name pad no. i/o function l0 99 l1 98 l2 97 l3 96 o these pins can be selected as lcd segment signal output pins (l0 to l3) or common signal output pins by the mask option. the common signal can be selected from among com1 to com4. l4 95 l5 94 l6 93 l7 92 l8 91 l9 90 l10 89 l11 88 l12 87 l13 86 l14 85 l15 84 l16 83 l17 82 l18 81 l19 80 l20 79 l21 78 l22 77 l23 76 l24 75 l25 74 l26 73 l27 72 l28 71 l29 70 l30 69 l31 68 o output pins dedicated to the lcd segment signal (l4 to l31). l32/ lp0.3 67 l33/ lp0.2 66 l34/ lp0.1 65 l35/ lp0.0 64 o these pins can be selected as lcd segment signal output pins (l32 to l35) or output port pins (lp0.0 to lp0.3) by the mask option. l36 28 l37 27 l38 26 lcd l39 25 o these pins can be selected as output pins dedicated to the lcd segment signal (l36 to l39) or common signal output pins by the mask option. the common signal can be selected from among com1 to com4.
fedl63611a-01 oki semiconductor ml63611a 18/49 table 2 pin description (basic functions) (continued) classification pin name pad no. i/o function l40 24 l41 23 l42 22 l43 21 l44 20 l45 19 l46 18 l47 17 l48 16 l49 15 l50 14 l51 13 l52 12 l53 11 l54 10 l55 9 l56 8 l57 7 l58 6 l59 5 l60 4 l61 3 l62 2 lcd l63 1 o output pins dedicated to the lcd segment signal (l40 to l63). rt0 29 resistance temperature sensor connection pin (for channel 0) crt0 30 resistance/capacitance tem perature sensor connection pin (for channel 0) rs0 31 reference resistor c onnection pin (for channel 0) cs0 32 o reference capacitor connec tion pin (for channel 0) in0 33 input pin for rc oscillator circuit (for channel 0) in1 34 i input pin for rc oscillator circuit (for channel 1) cs1 35 reference capacitor c onnection pin (for channel 1) rs1 36 reference resistor c onnection pin (for channel 1) a/d converter rt1 37 o resistance temperature sensor connection pin (for channel 1)
fedl63611a-01 oki semiconductor ml63611a 19/49 table 3 shows the secondary functi ons of each pin of the ml63611a table 3 pin description (secondary functions) classification pin name pad no. i/o function pb.0/int0 51 pb.1/int0 52 pb.2/int0 53 pb.3/int0 54 i external 0 interrupt input pins: the change of input signal level causes an interrupt to occur. the port b interrupt enable register (pbie) enables or disables an interrupt for each bit. pc.0/int1 55 pc.1/int1 56 pc.2/int1 57 pc.3/int1 58 i external 1 interrupt input pins: the change of input signal level causes an interrupt to occur. the port c interrupt enable register (pcie) enables or disables an interrupt for each bit. pe.3/int2 62 i external 2 interrupt input pin: the change of input signal level causes an interrupt to occur. p0.0/int5 43 p0.1/int5 44 p0.2/int5 45 external interrupt p0.3/int5 46 i external 5 interrupt input pins: the change of input signal level causes an interrupt to occur. the port 0 interrupt enabl e register (p0ie) enables or disables an interrupt for each bit. pb.0/tm0cap 51 timer 0 capture trigger input pin capture pb.1/tm1cap 52 i timer 1 capture trigger input pin pb.0/tm0ovf 51 timer 0 (tm0) overflow flag output pin pb.1/tm1ovf 52 o timer 1 (tm1) overflow flag output pin pb.2/t02ck 53 external clock input pin for timer 0 (tm0) and timer 2 (tm2) timer pb.3/t13ck 54 i external clock input pin for timer 1 (tm1) and timer 3 (tm3) pc.0/rxd 55 i serial port receive data input pin pc.1/txc 56 sync serial port clock input-output pin: transmit sync clock input-output pin when a serial port is used synchronously. transmit clock output when this device is used as a master processor. transmit clock input when this device is used as a slave processor. pc.2/rxc 57 i/o sync serial port clock input-output pin: receive sync clock input-output pin when a serial port is used synchronously. receive clock output when this device is used as a master processor. receive clock input when this device is used as a slave processor. serial port pc.3/txd 58 o serial port transmit data output pin pe.0/mon 59 o pin for monitoring the rc oscillation clock for the a/d converter pe.1/tbcclk 60 o low-speed oscillation clock (tbcclk) monitoring pin monitor pe.2/hsclk 61 o high-speed oscillation clock (hsclk) monitoring pin
fedl63611a-01 oki semiconductor ml63611a 20/49 power supply circuit configuration figures 6 through 9 show the power supply circuit configuration of option a to d. figure 6 option a power s upply circuit configuration osc1 osc0 halver circuit low-speed clock generator circuit 1/2v dd lcd bias circuit v/r2 0.7 v internal logic circuits (rom, ram, cpu, etc.) v hf v dd hc2 hc1 xt1 xt0 v dd3 v dd2 v dd1 c1 c2 v ss ceramic resonator 30 pf c l0 c l1 c xt 5 to 25 pf c 3 1.3 to 1.7 v fixed in the hardware v hf open v xt c g open open 0.1 p f 1.5 v c v high-speed clock generator circuit enosc (bit 1 of fcon) = ?0? or stv (bit 2 of adcon0) = ?0? v/r1 1.15 v c 2 32.768 khz 1.0 p f 1.0 p f 1.0 p f 1.0 p f 1.0 p f v xt enosc (bit 1 of fcon) = ?1? or stv (bit 2 of adcon0) = ?1? c ch v ch c 12 ml63611 a v ch
fedl63611a-01 oki semiconductor ml63611a 21/49 osc1 osc0 halver circuit low-speed clock generator circuit 1/2v dd lcd bias circuit v/r2 0.7 v internal logic circuits (rom, ram, cpu, etc.) v hf v dd hc2 hc1 xt1 xt0 v dd3 v dd2 v dd1 c1 c2 v ss ceramic resonator 30 pf c l0 c l1 c xt 5 to 25 pf c 3 1.3 to 1.7 v fixed in the hardware v hf open v xt c g open open 0.1 p f 1.5 v c v high-speed clock generator circuit enosc (bit 1 of fcon) = ?0? or stv (bit 2 of adcon0) = ?0? v/r1 1.15 v c 2 32.768 khz 1.0 p f 1.0 p f 1.0 p f 1.0 p f 1.0 p f v xt enosc (bit 1 of fcon) = ?1? or stv (bit 2 of adcon0) = ?1? c ch v ch c 12 ml63611 a v/r3 0.95 v v dd1 0.95 v min. 1.19 v max. c 1 1.0 p f v ch figure 7 option b power s upply circuit configuration
fedl63611a-01 oki semiconductor ml63611a 22/49 osc1 osc0 halver circuit low-speed clock generator circuit 1/2v dd lcd bias circuit v/r2 0.7 v internal logic circuits (rom, ram, cpu, etc.) v hf v dd hc2 hc1 xt1 xt0 v dd3 v dd2 v dd1 c1 c2 v ss ceramic resonator 30 pf c l0 c l1 c xt 5 to 25 pf c 3 1.8 to 3.6 v during heavy load (when v dd = 1.8 to 2.4 v) vh (bit 0 of vhcon) = ?1? v hf v xt c g 0.1 p f 3.0 v c v high-speed clock generator circuit en osc (bit 1 of fcon) = ?0? or stv ( bit 2 of adcon0) = ?0? v/r1 1.15 v c 1 32.768 khz 1.0 p f 1.0 p f 1.0 p f 1.0 p f 1.0 p f v xt enosc (bit 1 of fcon) = ?1? or stv ( bit 2 of adcon0) = ?1? c ch v ch c 12 ml63611 a software selection during normal load (when v dd = 2.4 to 3.6 v) vh (bit 0 of vhcon) = ?0? 0.1 p f c hf 0.1 p f c h12 v ch figure 8 option c power s upply circuit configuration
fedl63611a-01 oki semiconductor ml63611a 23/49 osc1 osc0 halver circuit low-speed clock generator circuit 1/2v dd lcd bias circuit v/r2 0.7 v internal logic circuits (rom, ram, cpu, etc.) v hf v dd hc2 hc1 xt1 xt0 v dd3 v dd2 v dd1 c1 c2 v ss ceramic resonator 30 pf c l0 c l1 c xt 5 to 25 pf c 3 1.8 to 3.6 v during heavy load (when v dd = 1.8 to 2.4 v) vh (bit 0 of vhcon) = ?1? v hf v xt c g 0.1 p f 3.0 v c v high-speed clock generator circuit enosc (bit 1 of fcon) = ?0? or stv (bit 2 of adcon0) = ?0? v/r1 1.15 v c 1 32.768 khz 1.0 p f 1.0 p f 1.0 p f 1.0 p f 1.0 p f v xt enosc (bit 1 of fcon) = ?1? or stv (bit 2 of adcon0) = ?1? c ch v ch c 12 ml63611 a software selection during normal load (when v dd = 2.4 to 3.6 v) vh (bit 0 of vhcon) = ?0? 0.1 p f c hf 0.1 p f c h12 c 2 1.0 p f v/r3 0.95 v v dd1 0.95 v min. 1.40 v max. v ch figure 9 option d power s upply circuit configuration
fedl63611a-01 oki semiconductor ml63611a 24/49 electrical characteristics (3.0 v) absolute maximum ratings (v ss = 0 v) parameter symbol condition rating unit power supply voltage 1 v dd1 ta = 25 q c ?0.3 to +1.8 v power supply voltage 2 v dd2 ta = 25 q c ?0.3 to +3.6 v power supply voltage 3 v dd3 ta = 25 q c ?0.3 to +5.4 v power supply voltage 4 v dd ta = 25 q c ?0.3 to +3.9 v power supply voltage 5 v hf ta = 25 q c ?0.3 to +3.9 v power supply voltage 6 v ch ta = 25 q c ?0.3 to +3.9 v power supply voltage 7 v xt ta = 25 q c ?0.3 to +3.9 v input voltage 1 v in1 v dd input, ta = 25 q c ?0.3 to v dd +0.3 v output voltage 1 v out1 v dd1 input, ta = 25 q c ?0.3 to v dd1 +0.3 v output voltage 2 v out2 v dd2 input, ta = 25 q c ?0.3 to v dd2 +0.3 v output voltage 3 v out3 v dd3 input, ta = 25 q c ?0.3 to v dd3 +0.3 v output voltage 4 v out4 v dd input, ta = 25 q c ?0.3 to v dd +0.3 v power dissipation p d ta = 25 q c 8 mw storage temperature t stg ? ?55 to +150 q c recommended operating conditions (v ss = 0 v) parameter symbol condition range unit operating temperature t op ? ?20 to +70 q c operating voltage v dd ? 1.8 to 3.6 v crystal oscillation frequency f xt c g = 5 to 25 pf 32.768k hz high-speed rc oscillator frequency f crh v dd = 1.8 to 3.6 v, r osh = 75 k : 700k r 30% hz high-speed ceramic oscillation frequency f ch v dd = 1.8 to 3.6 v 700k max. hz
fedl63611a-01 oki semiconductor ml63611a 25/49 dc characteristics (1) the regulator for the lcd bias reference is not used. (v dd = v dd2 = 3.0 v, v ss = 0 v, 1/3 bias, dspcnt = 0h, ta = ?20 to +70 q c unless otherwise specified) parameter symbol condition min. typ. max. unit measuring circuit supply current 1 i dd1 cpu in halt state, lcd is turned off (high-speed clock oscillation stopped) ? 0.53 1.2 a supply current 2 i dd2 cpu in halt state, lcd in power down mode (high-speed clock oscillation stopped) ? 0.45 0.9 a supply current 3 i dd3 cpu operating, lcd is turned off (low-speed clock oscillation; 32.768 khz crystal oscillation) ? 2 4 a supply current 4 i dd4 cpu operating (high-speed clock oscillation; approx. 700 khz rc oscillation) ? 450 700 a 1 the regulator for the lcd bias reference is used (v dd = 3.0 v, v ss = 0 v, 1/3 bias, dspcnt = 0h, ta = ?20 to +70 q c unless otherwise specified) parameter symbol condition min. typ. max. unit measuring circuit supply current 1 i dd1 cpu in halt state, lcd is turned off (high-speed clock oscillation stopped) ? 0.70 1.4 a supply current 2 i dd2 cpu in halt state, lcd in power down mode (high-speed clock oscillation stopped) ? 0.45 0.9 a supply current 3 i dd3 cpu operating, lcd is turned off (low-speed clock oscillation; 32.768 khz crystal oscillation) ? 2.2 4.5 a supply current 4 i dd4 cpu operating (high-speed clock oscillation; approx. 700 khz rc oscillation) ? 450 700 a 1
fedl63611a-01 oki semiconductor ml63611a 26/49 dc characteristics (2) the regulator for the lcd bias reference is not used (v dd = v dd 2 = 3.0 v, v ss = 0 v, ta = ?20 to +70 q c unless otherwise specified) parameter (pin name) symbol condition min. typ. max. unit measuring circuit v dd1 voltage v dd1 1/3 bias, 1/2 bias typ.?0.1 1/2 u v dd typ.+0.1 v v dd2 voltage v dd2 1/3 bias, 1/2 bias typ.?0.1 v dd typ.+0.1 v 1/3 bias typ.?0.2 3/2 u v dd typ.+0.2 v v dd3 voltage v dd3 1/2 bias (connected to v dd2 ) typ.?0.1 v dd typ.+0.1 v 1 the regulator for the lcd bias reference is used (v dd = 3.0 v, v ss = 0 v, ta = ?20 to +70 q c unless otherwise specified) parameter (pin name) symbol condition min. typ. max. unit measuring circuit v dd1 voltage v dd1 1/3 bias, 1/2 bias (ta = 25 q c) 0.85 0.95 1.05 v v dd1 voltage temperature deviation ' v dd1 ? ? ?4 ? mv/ q c 1/3 bias typ.?0.3 2 u v dd1 typ.+0.3 v v dd2 voltage v dd2 1/2 bias (connected to v dd1 ) typ.?0.2 v dd1 typ.+0.2 v 1/3 bias typ.?0.4 3 u v dd1 typ.+0.4 v v dd3 voltage v dd3 1/2 bias typ.?0.3 2 u v dd1 typ.+0.3 v 1
fedl63611a-01 oki semiconductor ml63611a 27/49 dc characteristics (3) (v dd = 3.0 v, v ss = 0 v, ta = ?20 to +70 q c unless otherwise specified) parameter (pin name) symbol condition min. typ. max. unit measuring circuit v hf voltage v hf ? ? 1/2 u v dd ? v (under a normal load) 0.8 1.15 1.5 v v ch voltage v ch (under a heavy load) v dd ?0.2 v dd v dd +0.1 v crystal oscillation start voltage v sta oscillation start time: within 5 seconds 1.8 ? ? v crystal oscillation hold voltage v hold ? 1.8 ? ? v external crystal oscillator capacitance c g ? 5 ? 25 pf internal crystal oscillator capacitance c d ? 20 25 30 pf external ceramic oscillator capacitance c l0, c l1 700khz ? 33 ? pf internal rc oscillator capacitance c os ? 8 12 16 pf 1 ld1 = 1, ld0 = 1, ta = 25 q c 2.5 2.6 2.7 v ? ld1 = 1, ld0 = 0, ta = 25 q c 2.3 2.4 2.5 v ld1 = 0, ld0 = 1, ta = 25 q c 1.9 2.0 2.1 v bld judgment voltage v bldc ld1 = 0, ld0 = 0, ta = 25 q c 1.7 1.8 1.9 v ta = ?20 to +25 q c ? 1.70 2.10 mv/ q c bld judgment voltage temperature deviation ' v bldc ta = +25 to +70 q c ? 1.50 2.00 mv/ q c
fedl63611a-01 oki semiconductor ml63611a 28/49 dc characteristics (4) (v dd = 3.0 v, v dd1 = 1.50 v, v dd2 = 3.00 v, v dd3 = 4.50 v, v ss = 0 v, ta = ?20 to +70 q c unless otherwise specified) parameter (pin name) symbol condition min. typ. max. unit measuring circuit output current 1 (pa.0 to pa.3) (pb.0 to pb.3) (pc.0 to pc.3) (pe.0 to pe.3) i oh1 v oh1 = v dd ?0.5 v ?6.0 ?3.5 ?1.0 ma i ol1 v ol1 = 0.5 v 1.0 3.5 6.0 ma i oh2 v oh2 = v dd ?0.7 v ?20.0 ?11.0 ?3.5 ma output current 2 (md, mdb) i ol2 v ol2 = 0.7 v 1.0 3.5 6.0 ma i oh3 v oh3 = v dd3 ?0.2 v (v dd3 level) ? ? ?4 p a i omh3 v omh3 = v dd2 +0.2 v (v dd2 level) 4 ? ? p a i omh3s v omh3s = v dd2 ?0.2 v (v dd2 level) ? ? ?4 p a i oml3 v oml3 = v dd1 +0.2 v (v dd1 level) 4 ? ? p a i oml3s v oml3s = v dd1 ?0.2 v (v dd1 level) ? ? ?4 p a output current 3 (l0 to l63) i ol3 v ol3 = v ss +0.2 v (v ss level) 4 ? ? p a i oh4 v oh4 = v dd ?0.5 v ?12.0 ?6.5 ?2.0 ma output current 4* (l32 to l35) i ol4 v ol4 = 0.5 v 1.0 3.5 6.0 ma i oh5r v oh5r = v dd ?0.5 v (rc oscillation) ?2.5 ?1.3 ?0.25 ma i ol5r v ol5r = 0.5 v (rc oscillation) 0.25 1.5 2.5 ma i oh5c v oh5c = v dd ?0.5 v (ceramic oscillation) ?500 ?250 ?100 p a output current 5 (osc1) i ol5c v ol5c = 0.5 v (ceramic oscillation) 200 500 800 p a i oh6 v oh6 = v dd ?0.1 v ?2.5 ?0.8 ?0.3 ma output current 6 (rt0, rt1, rs0, rs1, crt0, cs0, cs1) i ol6 v ol6 = 0.1 v 0.3 1.3 2.5 ma i ooh v oh = v dd ? ? 0.3 p a output leakage current (pa.0 to pa.3) (pb.0 to pb.3) (pc.0 to pc.3) (pe.0 to pe.3) i ool v ol = v ss ?0.3 ? ? p a 2 * applies only when l32 to l35 are selected as the output port in a mask option.
fedl63611a-01 oki semiconductor ml63611a 29/49 dc characteristics (5) (v dd = 3.0 v, v dd1 = 1.50 v, v dd2 = 3.00 v, v dd3 = 4.50 v, v ss = 0 v, ta = ?20 to +70 q c unless otherwise specified) parameter (pin name) symbol condition min. typ. max. unit measuring circuit i ih1 v ih1 = v dd (when pulled down) 7.5 50 100 a i il1 v il1 = v ss (when pulled up) ?100 ?50 ?7.5 a i ih1z v ih1 = v dd (in a high impedance state) 0 ? 1 a input current 1 (p0.0 to p0.3) (pa.0 to pa.3) (pb.0 to pb.3) (pc.0 to pc.3) (pe.0 to pe.3) i il1z v il1 = v ss (in a high impedance state) ?1 ? 0 a i il2 v il2 = v ss (when pulled up) ?350 ?170 ?30 a i ih2r v ih2r = v dd (rc oscillation) 0 ? 1 a i il2r v il2r = v ss (rc oscillation) ?1 ? 0 a i ih2c v ih2c = v dd (ceramic oscillation) 0.5 1.8 4.0 a input current 2 (osc0) i il2c v il2c = v ss (ceramic oscillation) ?4.0 ?1.8 ?0.5 a i ih3 v ih3 = v dd (when pulled down) 80 250 500 a i ih3z v ih3 = v dd (in a high impedance state) 0 ? 1 a input current 3 (in0, in1) i il3z v il3 = v ss (in a high impedance state) ?1 ? 0 a i ih4 v ih4 = v dd 150 1100 2400 a input current 4 (reset) i il4 v il4 = v ss ?1 ? 0 a i ih5 v ih5 = v dd 0.5 3.0 5.5 ma input current 5 (tst1, tst2) i il5 v il5 = v ss ?1.0 ? 0 p a 3
fedl63611a-01 oki semiconductor ml63611a 30/49 dc characteristics (6) (v dd = 3.0 v, v dd1 = 1.50 v, v dd2 = 3.00 v, v dd3 = 4.50 v, v ss = 0 v, ta = ?20 to +70 q c unless otherwise specified) parameter (pin name) symbol condition min. typ. max. unit measuring circuit v ih1 ? 2.4 ? 3.0 v input voltage 1 (p0.0 to p0.3) (pa.0 to pa.3) (pb.0 to pb.3) (pc.0 to pc.3) (pe.0 to pe.3) v il1 ? 0 ? 0.6 v v ih2 ? 2.4 ? 3.0 v input voltage 2 (osc0) v il2 ? 0 ? 0.6 v v ih3 ? 2.4 ? 3.0 v input voltage 3 (in0, in1) v il3 ? 0 ? 0.6 v v ih4 ? 2.4 ? 3.0 v input voltage 4 (reset, tst1, tst2) v il4 ? 0 ? 0.6 v hysteresis width 1 (p0.0 to p0.3) (pa.0 to pa.3) (pb.0 to pb.3) (pc.0 to pc.3) (pe.0 to pe.3) ' v t1 ? 0.2 0.5 1.0 v hysteresis width 2 (reset, tst1, tst2) ' v t2 ? 0.2 0.5 1.0 v 4 input pin capacitance (p0.0 to p0.3) (pa.0 to pa.3) (pb.0 to pb.3) (pc.0 to pc.3) (pe.0 to pe.3) c in ? ? ? 5 pf ?
fedl63611a-01 oki semiconductor ml63611a 31/49 measuring circuit 1 measuring circuit 2 input (*2) output a (*3) v ih v il v ss v dd v dd1 v dd2 v dd3 v ch v hf v xt *2 input logic circuit to determine a specified state. *3 to be repeated for the specified output pins. c ch , c ht , c xt , c 12 : 0.1 p f c 1 , c 2 , c 3 , c h12 : 1.0 p f c g : 15 pf c l0 , c l1 : 33 pf rt0 : 10 k : /2 k : cs0 : 820 pf ri0 : 10 k : ceramic resonator : 700khz v v c 1 c 3 v dd3 v dd1 v ss xt0 xt1 c h12 hc1 hc2 a v dd v c ch v ch c 12 c1 c2 v c 2 v dd2 c hf v hf v v xt c xt c g osc0 osc1 1 2 *1 rc oscillation 32.768 khz crystal ceramic oscillator 1 2 r osh 1 2 c l0 ceramic resonator rt0 cs0 ri0 rt0 cs0 in0 c l1
fedl63611a-01 oki semiconductor ml63611a 32/49 measuring circuit 3 input output a (*4) v ss v dd v dd1 v dd2 v dd3 v ch v hf v xt measuring circuit 4 input output waveform monitoring v ss v dd v dd1 v dd2 v dd3 v ch v hf v xt v ih v il (*4) *4 to be repeated for the specified input pins.
fedl63611a-01 oki semiconductor ml63611a 33/49 ac characteristics (serial interface, serial port) (v dd = 3.0 v, v ss = 0 v, ta = ?20 to +70 q c unless otherwise specified) synchronous communication parameter symbol condition min. typ. max. unit txc/rxc input fall time t f ? ? ? 1 s txc/rxc input rise time t r ? ? ? 1 s txc/rxc input ?l? level pulse width t cwl ? 0.8 ? ? s txc/rxc input ?h? level pulse width t cwh ? 0.8 ? ? s txc/rxc input cycle time t cyc ? 2 ? ? s txc/rxc output cycle time t cyc (0) cpu operating at 32.768 khz ? 30.5 ? s txd output delay time t ddr output load capacitance 10 pf ? ? 0.4 s rxd input setup time t ds ? 0.5 ? ? s rxd input hold time t dh ? 0.8 ? ? s synchronous communication timing (?h? level = 2.4 v, ?l? level = 0.6 v) txd (pc.3) rxd (pc.0) t cyc t dd t r t f t cwh t cwl t ddr t ds t ds t dh v dd v ss v dd v ss v dd v ss txc (pc.1)/ rxc (pc.2)
fedl63611a-01 oki semiconductor ml63611a 34/49 uart communication parameter symbol condition min. typ. max. unit transmit baud rate t brt t brt = 1/f brt t cr = 1/f osc t brt ?t cr t brt t brt +t cr s receive baud rate r brt r brt = 1/f brt r brt u 0.97 r brt r brt u 1.03 s f brt : baud rates (9600, 4800, 2400 and 1200 bps) uart communication timing (?h? level = 2.4 v, ?l? level = 0.6 v) t brt txd(pc.3) r brt rxd(pc.0) v ss v dd v ss v dd
fedl63611a-01 oki semiconductor ml63611a 35/49 ac characteristics (rc oscillation type a/d converter) (v dd = 3.0 v, v ss = 0 v, ta = ?20 to +70 q c unless otherwise specified) parameter (pin name) symbol condition min. typ. max. unit measuring circuit resistor for oscillation rs0, rs1, rt0, rt0-1, rt1 cs0, ct0, cs1 t 740 pf 1 ? ? k : input current limiting resistor ri0, rl1 ? 1 10 ? k : f osc1 resistor for oscillation = 2 k : 170 210 250 khz f osc2 resistor for oscillation = 10 k : 38.0 47.0 56.0 khz oscillation frequency f osc3 resistor for oscillation = 200 k : 2.30 2.80 3.30 khz kf1 rt0, rt0-1, rt1 = 2 k : 3.9 4.2 4.5 ? kf2 rt0, rt0-1, rt1 = 10 k : 0.990 1.0 1.010 ? rs x rt oscillation frequency ratio (*) kf3 rt0, rt0-1, rt1 = 200 k : 0.057 0.061 0.065 ? 5 * kfx is the ratio of the oscillation frequency by a sensor re sistor to the oscillation fre quency by a reference resistor in the same condition. kfx = (x = 1, 2, 3) measuring circuit 5 rt1 (crosc1) rs1 cs1 ri1 rt1 rs1 cs1 in1 ri0 cs0 rs0 in0 cs0 rs0 ct0 rt0 rt0 crt0 rt0-1 (crosc0) p0.0 p0.1 p0.2 p0.3 oscillation mode specified reset tst1 tst2 v dd d.u.t pe.0 frequency measurement (foscx) rt0,rt0-1,rt1=2 k : / 10 k : / 200 k : rs0,rs1=10 k : ri0,ri1=10 k : cs0,ct0,cs1 = 820 pf v ss f oscx (rt0 ? cs0 oscillation) f oscx (rs0 ? cs0 oscillation) , f oscx (rt0-1 ? cs0 oscillation) f oscx (rs0 ? cs0 oscillation) , f oscx (rt1 ? cs1 oscillation) f oscx (rs1 ? cs1 oscillation)
fedl63611a-01 oki semiconductor ml63611a 36/49 electrical characteristics (1.5 v) absolute maximum ratings (v ss = 0 v) parameter symbol condition rating unit power supply voltage 1 v dd1 ta = 25 q c ?0.3 to +1.8 v power supply voltage 2 v dd2 ta = 25 q c ?0.3 to +3.4 v power supply voltage 3 v dd3 ta = 25 q c ?0.3 to +5.1 v power supply voltage 4 v dd ta = 25 q c ?0.3 to +2.0 v power supply voltage 5 v ch ta = 25 q c ?0.3 to +2.0 v power supply voltage 6 v xt ta = 25 q c ?0.3 to +2.0 v input voltage 1 v in1 v dd input, ta = 25 q c ?0.3 to v dd +0.3 v output voltage 1 v out1 v dd1 input, ta = 25 q c ?0.3 to v dd1 +0.3 v output voltage 2 v out2 v dd2 input, ta = 25 q c ?0.3 to v dd2 +0.3 v output voltage 3 v out3 v dd3 input, ta = 25 q c ?0.3 to v dd3 +0.3 v output voltage 4 v out4 v dd input, ta = 25 q c ?0.3 to v dd +0.3 v power dissipation p d ta = 25 q c 1 mw storage temperature t stg ? ?55 to +150 q c recommended operating conditions (v ss = 0 v) parameter symbol condition range unit operating temperature t op ? ?20 to +70 q c operating voltage v dd ? 1.3 to 1.7 v crystal oscillation frequency f xt c g = 5 to 25 pf 32.768 k hz high-speed rc oscillator frequency f crh v dd = 1.3 to 1.7v, r osh = 200 k : 200 k r 30 % hz
fedl63611a-01 oki semiconductor ml63611a 37/49 dc characteristics (1) the regulator for the lcd bias reference is not used. ( v dd = v dd1 = 1.5 v, v ss = 0 v, 1/3 bias, dspcnt = 0h, ta = ?20 to +70 q c unless otherwise specified ) parameter symbol condition min. typ. max. unit measuring circuit supply current 1 i dd1 cpu in halt state, lcd is turned off (high-speed clock oscillation stopped) ? 1.4 2.8 a supply current 2 i dd2 cpu in halt state, lcd in power down mode (high-speed clock oscillation stopped) ? 0.9 1.8 a supply current 3 i dd3 cpu operating, lcd is turned off (low-speed clock oscillation; 32.768 khz crystal oscillation) ? 4.0 8.0 a supply current 4 i dd4 cpu operating (high-speed clock oscillation; approx. 200 khz rc oscillation) ? 80 150 a 1 the regulator for the lcd bias reference is used. (v dd = 1.5 v, v ss = 0 v, 1/3 bais, dspcnt = 0h, ta = ?20 to +70 q c unless otherwise specified) parameter symbol condition min. typ. max. unit measuring circuit supply current 1 i dd1 cpu in halt state, lcd is turned off (high-speed clock oscillation stopped) ? 1.6 3.0 a supply current 2 i dd2 cpu in halt state, lcd in power down mode (high-speed clock oscillation stopped) ? 0.9 1.8 a supply current 3 i dd3 cpu operating, lcd is turned off (low-speed clock oscillation; 32.768 khz crystal oscillation) ? 4.2 8.5 a supply current 4 i dd4 cpu operating (high-speed clock oscillation; approx. 200 khz rc oscillation) ? 80 150 a 1
fedl63611a-01 oki semiconductor ml63611a 38/49 dc characteristics (2) the regulator for the lcd bias reference is not used. (v dd = v dd 1 = 1.5 v, v ss = 0 v, ta = ?20 to +70 q c unless otherwise specified) parameter (pin name) symbol condition min. typ. max. unit measuring circuit v dd1 voltage v dd1 1/3 bias, 1/2 bias typ.?0.1 v dd typ.+0.1 v 1/3 bias typ.?0.2 2 u v dd typ.+0.2 v v dd2 voltage v dd2 1/2 bias (connected to v dd1 ) typ.?0.1 v dd typ.+0.1 v 1/3 bias typ.?0.3 3 u v dd typ.+0.3 v v dd3 voltage v dd3 1/2 bias typ.?0.2 2 u v dd typ.+0.2 v 1 the regulator for the lcd bias reference is used. (v dd = 1.5 v, v ss = 0 v, ta = ?20 to +70 q c unless otherwise specified) parameter (pin name) symbol condition min. typ. max. unit measuring circuit v dd1 voltage v dd1 1/3 bias, 1/2 bias (ta = 25 q c) 0.85 0.95 1.05 v v dd1 voltage temperature deviation ' v dd1 ? ? ?4 ? mv/ q c 1/3 bias typ.?0.3 2 u v dd1 typ.+0.3 v v dd2 voltage v dd2 1/2 bias (connected to v dd1 ) typ.?0.2 v dd1 typ.+0.2 v 1/3 bias typ.?0.4 3 u v dd1 typ.+0.4 v v dd3 voltage v dd3 1/2 bias typ.?0.3 2 u v dd1 typ.+0.3 v 1
fedl63611a-01 oki semiconductor ml63611a 39/49 dc characteristics (3) (v dd = 1.5 v, v ss = 0 v, ta = ?20 to +70 q c unless otherwise specified) parameter (pin name) symbol condition min. typ. max. unit measuring circuit (under a normal load) 0.8 1.15 1.5 v v ch voltage v ch (under a heavy load) v dd ?0.2 v dd v dd +0.1 v crystal oscillation start voltage v sta oscillation start time: within 5 seconds 1.3 ? ? v crystal oscillation hold voltage v hold ? 1.3 ? ? v external crystal oscillator capacitance c g ? 5 ? 25 pf internal crystal oscillator capacitance c d ? 20 25 30 pf internal rc oscillator capacitance c os ? 8 12 16 pf 1
fedl63611a-01 oki semiconductor ml63611a 40/49 dc characteristics (4) (v dd = 1.5 v, v dd1 =1.50 v, v dd2 = 3.00 v, v dd3 = 4.50 v, v ss = 0 v, ta = ?20 to +70 q c unless otherwise specified) parameter (pin name) symbol condition min. typ. max. unit measuring circuit i oh1 v oh1 = v dd ?0.5 v ?2.5 ?1.4 ?0.4 ma output current 1 (pa.0 to pa.3) (pb.0 to pb.3) (pc.0 to pc.3) (pe.0 to pe.3) i ol1 v ol1 = 0.5 v 0.4 1.4 2.5 ma i oh2 v oh2 = v dd ?0.7 v ?4.0 ?2.0 ?0.5 ma output current 2 (md,mdb) i ol2 v ol2 = 0.7 v 0.5 2.0 4.0 ma i oh3 v oh3 = v dd3 ?0.2 v (v dd3 level) ? ? ?4 p a i omh3 v omh3 = v dd2 +0.2 v (v dd2 level) 4 ? ? p a i omh3s v omh3s = v dd2 ?0.2 v (v dd2 level) ? ? ?4 p a i oml3 v oml3 = v dd1 +0.2 v (v dd1 level) 4 ? ? p a i oml3s v oml3s = v dd1 ?0.2 v (v dd1 level) ? ? ?4 p a output current 3 (l0 to l63) i ol3 v ol3 = v ss +0.2 v (v ss level) 4 ? ? p a i oh4 v oh4 = v dd ?0.5 v ?3.5 ?1.7 ?0.6 ma output current 4* (l32 to l35) i ol4 v ol4 = 0.5 v 0.4 1.4 2.5 ma i oh5r v oh5r = v dd ?0.5 v (rc oscillation) ?1.4 ?0.7 ?0.1 ma output current 5 (osc1) i ol5r v ol5r = 0.5 v (rc oscillation) 0.1 0.8 1.4 ma i oh6 v oh6 = v dd ?0.1 v ?1.1 ?0.4 ?0.1 ma output current 6 (rt0,rt1,rs0 , rs1,crt0, cs0,cs1) i ol6 v ol6 = 0.1 v 0.1 0.6 1.2 ma i ooh v oh = v dd ? ? 0.3 p a output leakage current (pa.0 to pa.3) (pb.0 to pb.3) (pc.0 to pc.3) (pe.0 to pe.3) i ool v ol = v ss ?0.3 ? ? p a 2 * applies only when l32 to l35 are selected as the output port in a mask option.
fedl63611a-01 oki semiconductor ml63611a 41/49 dc characteristics (5) (v dd = 1.5 v, v dd1 =1.50 v, v dd2 = 3.00 v, v dd3 = 4.50 v, v ss = 0 v, ta = ?20 to +70 q c unless otherwise specified) parameter (pin name) symbol condition min. typ. max. unit measuring circuit i ih1 v ih1 = v dd (when pulled down) 1.2 5.0 11.0 a i il1 v il1 = v ss (when pulled up) ?11.0 ?5.0 ?1.2 a i ih1z v ih1 = v dd (in a high impedance state) 0 ? 1 a input current 1 (p0.0 to p0.3) (pa.0 to pa.3) (pb.0 to pb.3) (pc.0 to pc.3) (pe.0 to pe.3) i il1z v il1 = v ss (in a high impedance state) ?1 ? 0 a i il2 v il2 = v ss (when pulled up) ?100 ?50 ?10 a i ih2r v ih2r = v dd (rc oscillation) 0 ? 1 a input current 2 (osc0) i il2r v il2r = v ss (rc oscillation) ?1 ? 0 a i ih3 v ih3 = v dd (when pulled up) 10 50 100 a i ih3z v ih3 = v dd (in a high impedance state) 0 ? 1 a input current 3 (in0, in1) i il3z v il3 = v ss (in a high impedance state) ?1 ? 0 a i ih4 v ih4 = v dd 10 180 350 a input current 4 (reset) i il4 v il4 = v ss ?1 ? 0 a i ih5 v ih5 = v dd 50 750 1500 a input current 5 (tst1, tst2) i il5 v il5 = v ss ?1.0 ? 0 p a 3
fedl63611a-01 oki semiconductor ml63611a 42/49 dc characteristics (6) (v dd = 1.5 v, v dd1 =1.50 v, v dd2 = 3.00 v, v dd3 = 4.50 v, v ss = 0 v, ta = ?20 to +70 q c unless otherwise specified) parameter (pin name) symbol condition min. typ. max. unit measuring circuit v ih1 ? 1.2 ? 1.5 v input voltage 1 (p0.0 to p0.3) (pa.0 to pa.3) (pb.0 to pb.3) (pc.0 to pc.3) (pe.0 to pe.3) v il1 ? 0 ? 0.3 v v ih2 ? 1.2 ? 1.5 v input voltage 2 (osc0) v il2 ? 0 ? 0.3 v v ih3 ? 1.2 ? 1.5 v input voltage 3 (in0, in1) v il3 ? 0 ? 0.3 v v ih4 ? 1.2 ? 1.5 v input voltage 4 (reset, tst1, tst2) v il4 ? 0 ? 0.3 v hysteresis width 1 (p0.0 to p0.3) (pa.0 to pa.3) (pb.0 to pb.3) (pc.0 to pc.3) (pe.0 to pe.3) ' v t1 ? 0.05 0.1 0.3 v hysteresis width 2 (reset, tst1, tst2) ' v t2 ? 0.05 0.1 0.3 v 4 input pin capacitance (p0.0 to p0.3) (pa.0 to pa.3) (pb.0 to pb.3) (pc.0 to pc.3) (pe.0 to pe.3) c in ? ? ? 5 pf ?
fedl63611a-01 oki semiconductor ml63611a 43/49 measuring circuit 1 c ch ,c xt c 1 ,c 2 ,c 3 ,c 12 c g rt0 cs0 ri0 v v ss xt0 xt1 : : : : : : 0.1 f 1.0 f 15 pf 10 k : / 2 k : 820 pf 10 k : a v dd v c 12 c1 c2 v c 2 c g osc0 osc1 (*1) 32.768 khz crystal *1 rc oscillation 1 r osh rt0 cs0 ri0 rt0 cs0 in0 v dd1 v dd2 v dd3 v ch v xt c 3 c ch c xt v c 1 1 2 2 measuring circuit 2 input (*2) output a (*3) v ih v il v ss v dd v dd1 v dd2 v dd3 v ch v hf v xt *2 input logic circuit to determine a specified state. *3 to be repeated for the specified output pins.
fedl63611a-01 oki semiconductor ml63611a 44/49 measuring circuit 3 input output a (*4) v ss v dd v dd1 v dd2 v dd3 v ch v hf v xt measuring circuit 4 input output waveform monitoring v ss v dd v dd1 v dd2 v dd3 v ch v hf v xt v ih v il (*4) *4 to be repeated for the specified input pins.
fedl63611a-01 oki semiconductor ml63611a 45/49 ac characteristics (serial interface, serial port) (v dd = 1.5 v, v ss = 0 v, ta = ?20 to +70 q c unless otherwise specified) synchronous communication parameter symbol condition min. typ. max. unit txc/rxc input fall time t f ? ? ? 1 s txc/rxc input rise time t r ? ? ? 1 s txc/rxc input ?l? level pulse width t cwl ? 0.8 ? ? s txc/rxc input ?h? level pulse width t cwh ? 0.8 ? ? s txc/rxc input cycle time t cyc ? 2 ? ? s txc/rxc output cycle time t cyc (0) cpu operating at 32.768 khz ? 30.5 ? s txd output delay time t ddr output load capacitance 10 pf ? ? 0.4 s rxd input setup time t ds ? 0.5 ? ? s rxd input hold time t dh ? 0.8 ? ? s synchronous communication timing (?h? level = 1.2 v, ?l? level = 0.3 v) txd (pc.3) rxd (pc.0) t cyc t dd t r t f t cwh t cwl t dd r t ds t ds t dh v dd v ss v dd v ss v dd v ss txc (pc.1)/ rxc (pc.2)
fedl63611a-01 oki semiconductor ml63611a 46/49 uart communication parameter symbol condition min. typ. max. unit transmit baud rate t brt t brt = 1/f brt t cr = 1/f osc t brt ?t cr t brt t brt +t cr s receive baud rate r brt r brt = 1/f brt r brt u 0.97 r brt r brt u 1.03 s f brt : baud rates (9600, 4800, 2400 and 1200bps) uart communication timing (?h? level = 1.2 v, ?l? level = 0.3 v) t brt txd(pc.3) r brt rxd(pc.0) v ss v dd v ss v dd
fedl63611a-01 oki semiconductor ml63611a 47/49 ac characteristics (rc oscillation type a/d converter) (v dd = 1.5 v, v ss = 0 v, ta = ?20 to +70 q c unless otherwise specified) parameter symbol condition min. typ. max. unit measuring circuit resistor for oscillation rs0, rs1, rt0, rt0-1, rt1 cs0, ct0, cs1 t 740 pf 1 ? ? k : input current limiting resistor ri0, ri1 ? 1 10 ? k : f osc1 resistor for oscillation = 2 k : 180 220 260 khz f osc2 resistor for oscillation = 10 k : 41.0 50.0 59.0 khz oscillation frequency f osc3 resistor for oscillation = 200 k : 2.30 2.80 3.30 khz kf1 rt0, rt0-1, rt1 = 2 k : 3.9 4.2 4.5 ? kf2 rt0, rt0-1, rt1 = 10 k : 0.990 1.0 1.010 ? rs x rt oscillation frequency ratio (*) kf3 rt0, rt0-1, rt1 = 200 k : 0.053 0.057 0.061 ? 5 kfx is the ratio of the oscillation frequency by a sensor resi stor to the oscillation frequency by a reference resistor in the same condition. kfx = (x = 1, 2, 3) measuring circuit 5 rt1 (crosc1) rs1 cs1 ri1 rt1 rs1 cs1 in1 ri0 cs0 rs0 in0 cs0 rs0 ct0 rt0 rt0 crt0 rt0-1 (crosc0) p0.0 p0.1 p0.2 p0.3 oscillation mode specified reset tst1 tst2 v dd d.u.t pe.0 frequency measurement (foscx) rt0,rt0-1,rt1=2 kw / 10 kw / 200 kw rs0,rs1=10 kw ri0,ri1=10 kw cs0,ct0,cs1 = 820 pf v ss f oscx (rs0 ? cs0 oscillation) , f oscx (rt0 ? cs0 oscillation) f oscx (rs0 ? cs0 oscillation) , f oscx (rt0-1 ? cs0 oscillation) f oscx (rt1 ? cs1 oscillation) f oscx (rs1 ? cs1 oscillation)
fedl63611a-01 oki semiconductor ml63611a 48/49 revision history page document no. date previous edition current edition description fedl63611a-01 jan 28. 2004 ? ? final edition 1
fedl63611a-01 oki semiconductor ml63611a 49/49 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. wh en planning to use the product, please ensure that the external conditions are reflected in the act ual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accide nt, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party?s industrial and intellectual prop erty right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this docu ment are intended for use in genera l electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not, unless specifi cally authorized by oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traf fic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of de termining the legality of export of these products and will take appropriate and necessary st eps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2004 oki electric industry co., ltd.

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